mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 637

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

16.9.9 Initializing the Serial Communication Controllers
The serial communication controllers require that a number of registers and parameters be
configured after power-on reset. To initialize SCC2, regardless of the protocol you are using,
follow these steps:
The buffer descriptors can have their R or E bits set at any time. Notice that the CPCR does
not need to be accessed after a power-on reset. A serial communication controller must be
disabled and reenabled after any dynamic change in its parallel I/O ports or serial channel
physical interface configuration. You can also use the RST bit in the CPCR (described in
Section 16.2.6.1 CPM Command Register) for a comprehensive reset.
Follow these steps to handle an interrupt in the serial communication controllers:
1. Set the parallel I/O ports to configure and connect the I/O pins to the SCC2.
2. Initialize the RAID field of the SDCR with the appropriate arbitration ID.
3. Set the port C registers to configure the CTSx and CDx pins to be in parallel I/O with
4. If the time-slot assigner is used, you must configure the serial interface. If the SCC2 is
5. Set the GSMR_H and GSMR_L, but do not write the ENT or ENR bits yet.
6. Set the PSMR.
7. Set the DSR.
8. Initialize the required values for the SCC2 in its parameter RAM.
9. Clear any current events in the SCCE register (optional).
10. Set the SCCM register to enable the interrupts in the SCCE register.
11. Set the CICR to configure the SCC2 interrupt priority.
12. Clear any current interrupts in the CIPR (optional).
13. Set the CIMR to enable interrupts to the CPM interrupt controller.
14. Set the ENT and ENR bits in the GSMR_L.
1. Once an interrupt occurs, read the SCCE register to locate the source of the interrupt.
2. Process the TX buffer descriptors to reuse them if the TX or TXE bit was set in the
3. Extract data from the RX buffer descriptor if the RX, RXB, or RXF bit is set in the SCCE
interrupt capability or to be direct connections to the SCC2 (if modem support is
needed).
in NMSI mode, the SICR must still be initialized.
The SCCE bits to be “handled” in this interrupt handler are normally cleared at this time
by writing ones to them.
SCCE register. If the transmit speed is fast or the interrupt delay is long, more than
one transmit buffer may have been sent by a serial communication controller. Thus, it
is important to check more than just one TX buffer descriptor during interrupt handling.
One common practice is to process all TX buffer descriptors in the interrupt handler
until one is found with its R bit set.
register. If the receive speed is fast or the interrupt delay is long, more than one
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Communication Processor Module
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