mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 719

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

Freescale Semiconductor, Inc.
Communication Processor Module
If the CM bit in the TX buffer descriptor is set, the SCCx ASYNC HDLC controller writes the
signal unit status bits into the buffer descriptor after transmission, but it does not clear the R
bit. The SCCx ASYNC HDLC controller then proceeds to the next TX buffer descriptor in the
table. If it is not ready, it waits until it is ready. While the SCCx ASYNC HDLC controller is
transmitting data from the buffers, it automatically performs the transparency encoding
specified by the protocol. This encoding is described in Section 16.9.19.4 Transmitter
Transparency Encoding .
BOF
A
C
I
FCS
EOF
M * 8 BITS
8 BITS
8 BITS
8 BITS
2 * 8 BITS
8 BITS
Figure 16-89. ASYNC HDLC Frame Structure
You must issue the STOP TRANSMIT command to rearrange the transmit queue before the
communication processor module finishes transmitting all the buffers. This can be useful
when transmitting expedited data prior to previously linked buffers or for error situations.
When the SCCx ASYNC HDLC controller receives the STOP TRANSMIT command, it stops
transmitting and sends the abort sequence. It then transmits idle characters until the
RESTART TRANSMIT command is given, at which point it resumes transmission with the
next TX buffer descriptor.
16.9.19.3 SCCX ASYNC HDLC CHANNEL FRAME RECEPTION PROCESS. The SCCx
ASYNC HDLC receiver is designed to operate with a minimum amount of intervention from
the core and can decode the transparency characters, check the CRC of the frame, and
detect errors on the line and in the controller. When the core enables the receiver, the
receiver waits for data to be present on the line. When the receiver detects a data byte of
the incoming frame that was preceded by one or more opening flags, the SCCx ASYNC
HDLC controller fetches the next buffer descriptor and if the E bit is set it starts transferring
the incoming frame into the buffer descriptor associated data buffer. When the data buffer
is full, the SCCx ASYNC HDLC controller clears the E bit in the buffer descriptor. If the
incoming frame exceeds the length of the data buffer, the SCCx ASYNC HDLC controller
fetches the next buffer descriptor in the table and, if empty, continues transferring the rest
of the frame into the associated data buffer.
During this process, the receiver automatically decodes the transparency character required
of the SCCx ASYNC HDLC protocol. This procedure is described in detail in
Section 16.9.19.5 Receiver Transparency Decoding . When the frame ends, the
controller checks the incoming CRC field and writes it to the data buffer. It then writes the
length of the entire frame to the DATA LENGTH field of the last buffer descriptor. The SCCx
ASYNC HDLC controller sets the L bit, writes the frame status bits into the buffer descriptor,
and clears the E bit if the CM bit is clear. It then sets the RXF bit in the SCCE–ASYNC HDLC
register, which indicates that a frame has been received and is in memory. The SCCx
ASYNC HDLC controller then waits for the start of the next frame which may or may not have
an opening flag.
MPC823 REFERENCE MANUAL
16-267
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