upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 108

• Manufacturer Part Number: upd70f3422gj-gae-qs-ax
• Description: 32-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

Chapter 3
108
Initial Value
Table 3-4
Caution
Access
Note
(1)
(2)
PC - Program counter
The program counter holds the instruction address during program execution.
The lower 26 bits are valid, and bits 31 to 26 are fixed to 0. If a carry occurs
from bit 25 to 26, it is ignored. Branching to an odd address cannot be
performed. Bit 0 is fixed to 0.
This register can not be accessed by any instruction.
0000 0000
EIPC, FEPC, DBPC, CTPC - PC saving registers
The PC saving registers save the contents of the program counter for different
occasions, see Table 3-4.
When one of the occasions listed in Table 3-4 occurs, except for some
instructions, the address of the instruction following the one being executed is
saved to the saving registers.
For more details refer to Table 3-9 on page 112 and to the “Interrupt Controller
(INTC)“ on page 187.
All PC saving registers are built up as the PC, with the initial value 0xxx xxxx
(x = undefined).
PC saving registers
When multiple interrupt servicing is enabled, the contents of EIPC or FEPC
must be saved by program—because only one PC saving register for
maskable interrupts and non-maskable interrupts is provided, respectively.
When setting the value of any of the PC saving registers, use even values
(bit 0 = 0). If bit 0 is set to 1, the setting of this bit is ignored.
This is because bit 0 of the program counter is fixed to 0.
Preliminary User’s Manual U17566EE1V2UM00
a)
31
Register
Status saving register
during interrupt
Status saving register
during non-maskable
interrupts
Status saving register
during exception/debug
trap
Status saving register
during CALLT execution
Reading from this register is only enabled between a DBTRAP exception (excep-
tion handler address 0000 0060
instruction. DBTRAP exceptions are generated upon ILGOP and ROM Correction
detections (refer to “Interrupt Controller (INTC)“ on page 187 and “ROM Correction
Function (ROMC)“ on page 331).
fixed to 0
H
. The program counter is cleared by any reset.
26
25
Shortcut Saves contents of PC in case of
EIPC
FEPC
DBPC
CTPC
instruction address during execution
a
H
) and the exception handler terminating DBRET
• software exception
• maskable interrupt
• non-maskable interrupt
• exception trap
• debug trap
• debug break
• during a single-step operation
• execution of CALLT instruction
CPU System Functions
1
0
0
H