upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 596

• Manufacturer Part Number: upd70f3422gj-gae-qs-ax
• Description: 32-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

Chapter 18
596
Figure 18-8
18.6.3 Transfer direction specification
18.6.4 Acknowledge signal (ACK)
INTIICn
SDAn
SCLn
Note
In addition to the 7-bit address data, the master device sends 1 bit that
specifies the transfer direction. When this transfer direction specification bit
has a value of 0, it indicates that the master device is transmitting data to a
slave device. When the transfer direction specification bit has a value of 1, it
indicates that the master device is receiving data from a slave device.
Transfer direction specification
The INTIICn signal is generated if a local address or extension code is
received during slave device operation.
The acknowledge signal (ACK) is used by the transmitting and receiving
devices to confirm serial data reception.
The receiving device returns one ACK signal for each 8 bits of data it receives.
The transmitting device normally receives an ACK signal after transmitting 8
bits of data. However, when the master device is the receiving device, it does
not output an ACK signal after receiving the final data to be transmitted. The
transmitting device detects whether or not an ACK signal is returned after it
transmits 8 bits of data. When an ACK signal is returned, the reception is
judged as normal and processing continues. If the slave device does not return
an ACK signal, the master device outputs either a stop condition or a restart
condition and then stops the current transmission. Failure to return an ACK
signal may be caused by the following two factors.
(a)
(b)
When the receiving device sets the SDAn line to low level during the ninth
clock, the ACK signal becomes active (normal receive response).
When the IICCn.ACKEn bit is set to 1, automatic ACK signal generation is
enabled.
Transmission of the eighth bit following the 7 address data bits causes the
IICSn.TRCn bit to be set. When this TRCn bit’s value is 0, it indicates receive
mode. Therefore, the ACKEn bit should be set to 1.
When the slave device is receiving (when TRCn bit = 0), if the slave device
does not need to receive any more data after receiving several bytes, clearing
Preliminary User’s Manual U17566EE1V2UM00
Reception was not performed normally.
The final data was received.
AD6
1
AD5
2
AD4
3
AD3
4
AD2
5
AD1
Transfer direction specification
6
AD0
7
R/W
8
9
Note
I
2
C Bus (IIC)