upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 257

• Manufacturer Part Number: upd70f3422gj-gae-qs-ax
• Description: 32-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

Bus and Memory Control (BCU, MEMC)
Caution
7.2.4 NPB access timing
7.2.5 Bus properties
(1)
(2)
All accesses to the peripheral I/O areas are passed over to the NPB bus via
the VSB - NPB bus bridge BBR. Read and write access times to registers via
the NPB depend on the register (refer to “Registers Access Times” on
page 911), the system clock VBCLK and the setting of the VSWC register.
The CPU operation during an access to a register via the NPB depends also
on the kind of peripheral I/O area:
• Fixed peripheral I/O area
• Programmable peripheral I/O area
Pay attention at write accesses to NPB peripheral I/O registers via the
programmable peripheral I/O area.
Since the CPU may continue operation, even though the data has not yet been
transferred to its destination register, inconsistencies may occur between the
program flow and the status of the registers.
In particular register set-ups which change an operational status of a certain
module require special notice, like, for instance, masking/unmasking of
interrupts via maskable interrupt control registers xxIC, enabling/disabling
timers, etc.
This section summarizes the properties of the external bus.
Bus width
The microcontroller device accesses external memory and external I/O in 8-bit,
16-bit, or 32-bit units.
The data bus size for each chip select area is specified in the local bus size
configuration register (LBS).
The operation for each type of access is given in “Access to 8-bit data busses”
on page 296 and in “Access to 16-bit data busses” on page 302.
Bus priority order
There are three kinds of external bus cycles as shown below. The DMA cycle
has the highest priority, followed by the operand data access, and instruction
fetch, in that order.
Preliminary User’s Manual U17566EE1V2UM00
During a read or write access the CPU operation stops until the access via
the NPB is completed.
During a read access the CPU operation stops until the read access via the
NPB is completed.
During a write access the CPU operation continues operation, provided any
preceded NPB access is already finished. If a preceded NPB access is still
ongoing the CPU stops until this access is finished and the NPB is cleared.
Chapter 7
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