upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 593
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upd70f3422gj-gae-qs-ax
Manufacturer Part Number
upd70f3422gj-gae-qs-ax
Description
32-bit Single-chip Microcontroller
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.UPD70F3422GJ-GAE-QS-AX.pdf
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I
2
C Bus (IIC)
(Clock input)
Clock output
Data output
Data input
Figure 18-4
18.5 I
18.6 I
Master device
The serial clock pin (SCLn) and serial data bus pin (SDAn) are configured as
follows.
SCLn
SDAn
Since outputs from the serial clock line and the serial data bus line are N-ch
open-drain outputs, an external pull-up resistor is required.
Pin configuration diagram
The following section describes the I
and the signals used by the I
Preliminary User’s Manual U17566EE1V2UM00
2
2
C Bus Pin Functions
C Bus Definitions and Control Methods
SCLn
SDAn
This pin is used for serial clock input and output.
This pin is an N-ch open-drain output for both master and
slave devices. Input is Schmitt input.
This pin is used for serial data input and output.
This pin is an N-ch open-drain output for both master and
slave devices. Input is Schmitt input.
PORTV
PORTV
DD
DD
2
C bus. The transfer timing for the “start
SDAn
SCLn
2
C bus’s serial data communication format
Slave device
(Clock output)
Clock input
Data output
Data input
Chapter 18
593
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