upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 225

• Manufacturer Part Number: upd70f3422gj-gae-qs-ax
• Description: 32-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

Interrupt Controller (INTC)
Figure 5-15
5.7 Multiple Interrupt Processing Control
(2)
Restore
Recovery from a debug trap is carried out by the DBRET instruction. By
executing the DBRET instruction, the CPU carries out the following processing
and controls the address of the restored PC.
(1) Loads the restored PC and PSW from DBPC and DBPSW.
(2) Transfers control to the address indicated by the restored PC and PSW.
Figure 5-15 illustrates the restore processing from a debug trap.
Restore processing from debug trap
Multiple interrupt processing control is a process by which an interrupt request
that is currently being processed can be interrupted during processing if there
is an interrupt request with a higher priority level, and the higher priority
interrupt request is received and processed first.
If there is an interrupt request with a lower priority level than the interrupt
request currently being processed, that interrupt request is held pending.
Maskable interrupt multiple processing control is executed when an interrupt
has an enable status (ID = 0). Thus, if multiple interrupts are executed, it is
necessary to have an interrupt enable status (ID = 0) even for an interrupt
processing routine.
If a maskable interrupt enable or a software exception is generated in a
maskable interrupt or software exception service program, it is necessary to
save EIPC and EIPSW.
This is accomplished by the following procedure.
Preliminary User’s Manual U17566EE1V2UM00
PC
PSW
Jump to address of restored PC
DBRET instruction
DBPC
DBPSW
Chapter 5
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