upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 279

• Manufacturer Part Number: upd70f3422gj-gae-qs-ax
• Description: 32-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

Bus and Memory Control (BCU, MEMC)
(immediately preceding
Internal address latch
Figure 7-5
Output address
address)
7.4 Page ROM Controller
(1)
Page ROM address
In page ROM mode the microcontroller reads consecutive data from one page
by inserting the wait cycles defined by PRC.PRW[2:0] instead of wait cycles
defined in registers DWC0 and DWC1.
The page ROM controller decides whether a page ROM cycle is on-page or
off-page. To do so, it buffers the address of the previous cycle and compares it
with the address of the current cycle. If the compare result proves that the read
access is on-page the read cycle is performed with wait cycles defined by
PRC.PRW[2:0].
In the page ROM configuration register (PRC), one or more of the address bits
(A3 to A6) are set as masking addresses (no comparison is made for these
addresses). The masking address is chosen according to the configuration of
the connected page ROM and the number of continuously readable bits.
Wait control for normal access (off-page) and page access (on-page) is
specified by different registers: For page access, wait control is performed
according to PRC register setting. For normal access, wait control is performed
according to DWC0 and DWC1 register settings.
The following figures show the on-page/off-page judgment during page ROM
connection for a 16-Mbit page ROM and for different data bus widths.
8-bit data bus width
The page size or the number of continuously readable bits is 32 x 8 bit. To
provide 32 addresses, a 5-bit on-page address is required. Therefore, set
PRC.MA[6:3] = 0011
16-Mbit page ROM (2 M × 8 bits), page size 32 x 8 bit
Preliminary User’s Manual U17566EE1V2UM00
A22
A22
A21
...
A20
A20
...
A19
A19
...
B
.
Comparison
Off-page address
A7
A7
A7
MA6
A6
A6
A6
0
MA5
A5
A5
A5
0
MA4
A4
A4
A4
1
MA3
A3
A3
A3
On-page address
1
A2
PRC register setting
A2
A1
A1
Chapter 7
A0
A0
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