upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 557

• Manufacturer Part Number: upd70f3422gj-gae-qs-ax
• Description: 32-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

Clocked Serial Interface (CSIB)
Shift register
INTCBnRE
INTCBnR
CBnOVE
17.4.5 Continuous reception mode (error)
CBnTSF
CBnRX
SCKBn
SOBn
SIBn
L
(1)
(2)
(3)
(4)
(8) Check that the CBnSTR.CBnTSF bit = 0 and set the CBnPWR bit to 0 to
To continue transfer, repeat steps (5) and (6) before (7).
MSB first (CBnCTL0.CBnDIR bit = 0), communication type 2 (see 16.4 (2)
CSIBn control register 1 (CBnCTL1)), transfer data length = 8 bits
(CBnCTL2.CBnCL3 to CBnCTL2.CBnCL0 bits = 0, 0, 0, 0)
(1) Clear the CBnCTL0.CBnPWR bit to 0.
(2) Set the CBnCTL1 and CBnCTL2 registers to specify the transfer mode.
(3) Set the CBnCTL0.CBnRXE bit to 1 at the same time as specifying the
(4) Set the CBnPWR bit = 1 to enable CSIBn operation.
(5) Perform a dummy read of the CBnRX register (reception start trigger).
(6) The reception complete interrupt request signal (INTCBnR) is output.
(7) If the data could not be read before the end of the next transfer, the
(8) Overrun error processing is performed after checking that the
(9) Clear CBnOVE bit to 0.
(10)Check that the CBnSTR.CBnTSF bit = 0 and set the CBnPWR bit to 0 to
Preliminary User’s Manual U17566EE1V2UM00
stop the operation of CSIBn (end of reception).
transfer mode using the CBnDIR bit, to set the reception enabled status.
CBnSTR.CBnOVE flag is set to 1 upon the end of reception and the
reception error interrupt INTCBnRE is output.
CBnOVE bit = 1 in the INTCBnRE interrupt servicing.
stop the operation CSIBn (end of reception).
(5)
0
1
0
1
0
1
0
(6)
1
55H
1
0
1
55H
0
1
0
1
(7)
(8) (9) (10)
0
AAH
AAH
00H
00H
Chapter 17
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