upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 210

• Manufacturer Part Number: upd70f3422gj-gae-qs-ax
• Description: 32-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

Chapter 5
210
Bit position
xxIC
2 to 0
7
6
xxIF
7
5.3.4 xxIC - Maskable interrupts control register
Bit name
xxPR2 to
Note
xxPR0
xxMK
xxIF
xxMK
6
An interrupt control register is assigned to each interrupt request (maskable
interrupt) and sets the control conditions for each maskable interrupt request.
This register can be read/written in 8-bit or 1-bit units.
xx: identification name of each peripheral unit (VC0-VC1, WT0UV-WT1UV,
TM01, P0-P7, TZ0UV-TZ9UV, TP0OV-TP3OV, TP0CC0-TP3CC0, TP0CC1-
TP3CC1, TG0OV0-TG2OV0, TG0OV1-TG2OV1, TG0CC0-TG2CC0,
TG0CC1-TG2CC1, TG0CC2-TG2CC2, TG0CC3-TG2CC3, TG0CC4-
TG2CC4, TG0CC5-TG2CC5, AD, C0ERR, C1ERR, C0WUP, C1WUP, C0REC,
C1REC, C0TRX, C1TRX, CB0RE-CB2RE, CB0R-CB2R, CB0T-CB2T, UA0RE-
UA1RE, UA0R-UA1R, UA0T-UA1T, IIC0-IIC1, DMA0-DMA3, INT70, INT71,
LCD)
The address and bit of each interrupt control register are shown in the
following table.
Preliminary User’s Manual U17566EE1V2UM00
Function
This is an interrupt request flag.
The flag xxIFn is reset automatically by the hardware if an interrupt request is
acknowledged.
This is an interrupt mask flag.
8 levels of priority order are specified for each interrupt.
0: Interrupt request not issued
1: Interrupt request issued
0: Enables interrupt processing
1: Disables interrupt processing (pending)
5
0
xxPR2
0
0
0
0
1
1
1
1
4
0
xxPR1
0
0
1
1
0
0
1
1
3
0
xxPR0
0
1
0
1
0
1
0
1
xxPR2
2
Interrupt priority specification bit
Specifies level 0 (highest)
Specifies level 1
Specifies level 2
Specifies level 3
Specifies level 4
Specifies level 5
Specifies level 6
Specifies level 7 (lowest)
xxPR1
1
xxPR0
0
Interrupt Controller (INTC)
FFFF F110H to
FFFF F18EH
Address
value
Initial
47H