upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 367
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upd70f3422gj-gae-qs-ax
Manufacturer Part Number
upd70f3422gj-gae-qs-ax
Description
32-bit Single-chip Microcontroller
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.UPD70F3422GJ-GAE-QS-AX.pdf
(930 pages)
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16-bit Timer/Event Counter P (TMP)
TIPn0 pin
(external event
count input)
INTTPnCC0 signal
TPnCCR0 register
16-bit counter
Figure 11-8
Figure 11-9
TPnCE bit
FFFFH
0000H
Caution
11.5.2 External event count mode (TPnMD2 to TPnMD0 = 001)
In the external event count mode, the valid edge of the external event count
input is counted when the TPnCTL0.TPnCE bit is set to 1, and an interrupt
request signal (INTTPnCC0) is generated each time the specified number of
edges have been counted. The TOPn0 pin cannot be used.
Usually, the TPnCCR1 register is not used in the external event count mode.
Configuration in external event count mode
Basic timing in external event count mode
This figure shows the basic timing when the rising edge is specified as the
valid edge of the external event count input.
Preliminary User’s Manual U17566EE1V2UM00
External
event
count
interval
(D0)
Edge
detector
D
0
TPnCE bit
External
event
count
interval
(D0 + 1)
D
D
0
0
External
event
count
interval
(D0 + 1)
D
0
CCR0 buffer register
TPnCCR0 register
16-bit counter
INTTPnCC0 signal
TPnCCR0 register
(TIPn0 pin input)
External event
Clear
16-bit counter
count input
Match signal
D
0
− 1
D
D
0
INTTPnCC0 signal
0
0000
Chapter 11
0001
367
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