upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 624

• Manufacturer Part Number: upd70f3422gj-gae-qs-ax
• Description: 32-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

Chapter 18
624
18.15.1 Master operation 1
18.14 Cautions
18.15 Communication Operations
(1)
(2)
When IICFn.STCENn bit = 0
Immediately after the I
status (IICFn.IICBSYn bit = 1) is recognized regardless of the actual bus
status. To execute master communication in the status where a stop condition
has not been detected, generate a stop condition and then release the bus
before starting the master communication.
Use the following sequence for generating a stop condition.
<1> Set the IICCLn register.
<2> Set the IICCn.IICEn bit.
<3> Set the IICCn.SPTn bit.
When IICFn.STCENn bit = 1
Immediately after I
(IICBSYn bit = 0) is recognized regardless of the actual bus status. To issue
the first start condition (IICCn.STTn bit = 1), it is necessary to confirm that the
bus has been released, so as to not disturb other communications.
The following shows the flowchart for master communication when the
communication reservation function is enabled (IICFn.IICRSVn bit = 0) and the
master operation is started after a stop condition is detected
(IICFn.STCENn bit = 0).
Preliminary User’s Manual U17566EE1V2UM00
2
C0n operation is enabled, the bus released status
2
C0n operation is enabled, the bus communication
I
2
C Bus (IIC)