upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 664

• Manufacturer Part Number: upd70f3422gj-gae-qs-ax
• Description: 32-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

Chapter 19
664
Figure 19-20
CAN bus
Bit timing
(3)
Interframe space
Synchronizing data bit
• The receiving node establishes synchronization by a level change on the
• The transmitting node transmits data in synchronization with the bit timing of
(a) Hardware synchronization
This synchronization is established when the receiving node detects the start
of frame in the interframe space.
• When a falling edge is detected on the bus, that TQ means the sync
Adjusting synchronization of data bit
(b) Resynchronization
Synchronization is established again if a level change is detected on the bus
during reception (only if a recessive level was sampled previously).
• The phase error of the edge is given by the relative position of the detected
• The sample point of the data of the receiving node moves relatively due to
Preliminary User’s Manual U17566EE1V2UM00
bus because it does not have a sync signal.
the transmitting node.
segment and the next segment is the prop segment. In this case,
synchronization is established regardless of SJW.
edge and sync segment.
the “discrepancy” in the baud rate between the transmitting node and
receiving node.
<Sign of phase error>
0:
Positive:
Negative:
If phase error is positive: Phase segment 1 is longer by specified SJW.
If phase error is negative: Phase segment 2 is shorter by specified SJW.
Sync
segment
If the edge is within the sync segment
If the edge is before the sample point (phase error)
If the edge is after the sample point (phase error)
Prop
segment
Start of frame
Phase
segment 1
Phase
segment 2
CAN Controller (CAN)