upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 512

• Manufacturer Part Number: upd70f3422gj-gae-qs-ax
• Description: 32-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

Chapter 16
512
Bit position
3, 2
1
0
Table 16-3
UAnPS[1:0]
Note
Bit name
UAnCL
UAnSL
(2)
(3)
UAnCTL0 register contents (2/2)
For details of parity, see “Parity types and operations“ on page 530.
UAnCTL1 - UARTAn control register 1
The UAnCTL1 register is an 8-bit register used to select the input clock for the
UARTAn.
For details, see “UAnCTL1 - UARTAn control register 1“ on page 534.
UAnCTL2 - UARTAn control register 2
The UAnCTL2 register is an 8-bit register used to control the baud rate for the
UARTAn.
For details, see “UAnCTL2 - UARTAn control register 2“ on page 535.
Preliminary User’s Manual U17566EE1V2UM00
Function
Parity selection
• This register is rewritten only when the UAnPWR bit = 0 or the UAnTXE bit =
• If “Reception with 0 parity” is selected during reception, a parity check is not
• When transmission and reception are performed in the LIN format, clear the
Specification of data character length of 1 frame of transmit/receive data
This register can be rewritten only when the UAnPWR bit = 0 or the UAnTXE bit =
the UAnRXE bit = 0.
Specification of length of stop bit for transmit data
This register can be rewritten only when the UAnPWR bit = 0 or the UAnTXE bit =
the UAnRXE bit = 0.
0: 7 bits
1: 8 bits
0: 1 bit
1: 2 bits
the UAnRXE bit = 0.
performed.
Therefore, since the UAnSTR.UAnPE bit is not set, no error interrupt is
output.
UAnPS1 and UAnPS0 bits to 00.
UAnPS1
0
0
1
1
UAnPS0
0
1
0
1
No parity output
0 parity output
Odd parity output
Even parity output Even parity check
transmission
Asynchronous Serial Interface (UARTA)
Parity selection during
Reception with no parity
Reception with 0 parity
Odd parity check
reception