upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 850

• Manufacturer Part Number: upd70f3422gj-gae-qs-ax
• Description: 32-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

Chapter 24
850
Figure 24-4
Example
24.3.2 Generating the volume information
Note
(2)
Tone frequency calculation
The tone frequency can be calculated as:
where:
f
[SG0FL buffer] = contents of the SG0FL buffer
[SG0FH buffer] = contents of the SG0FH buffer
If:
then:
Note that the buffer contents can differ from the contents of the associated
register until the next compare match.
The sound volume information is generated by comparing the SG0FL counter
value with the contents of the SG0PWM volume buffer. An RS flipflop is set
when the counter matches the SG0FL buffer and reset when the counter
reaches the value of the volume buffer SG0PWM.
PWM signal generation
The duty cycle of the PWM signal is determined by the difference between the
contents of the SG0FL counter buffer and the contents of the SG0PWM
volume buffer. The larger the difference, the smaller the duty cycle.
The PWM signal is continually high when the value of the volume buffer is
higher than the value of the frequency compare buffer.
Preliminary User’s Manual U17566EE1V2UM00
SG0CLK
– f
– [SG0FL buffer] = 255 (00FF
– [SG0FH buffer] = 32 (0020
– f
f
tone
SG0FL
counter
value
PWM
signal
(RS flip-
flop output)
SG0CLK
tone
= frequency of the SG0 input clock
= f
= 947 Hz
SG0CLK
= 16 MHz
/ (([SG0FL buffer] + 1) × ([SG0FH buffer] + 1) × 2)
H
H
)
) (this yields a PWM frequency of 62.5 KHz)
SG0PWM buffer value
(when reached, resets the FF)
SG0FL buffer value
(when reached, sets the FF)
t
Sound Generator (SG)