upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 508
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upd70f3422gj-gae-qs-ax
Manufacturer Part Number
upd70f3422gj-gae-qs-ax
Description
32-bit Single-chip Microcontroller
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.UPD70F3422GJ-GAE-QS-AX.pdf
(930 pages)
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Chapter 16
508
PCLK8 (62.5kHz)
PCLK1 (8MHz)
PCLK2 (4MHz)
INTUAnRE
Figure 16-1
INTUAnR
INTUAnT
16.2 Configuration
Note
• 13 to 20 bits selectable for the SBF (Sync Break Field) in the LIN (Local
• DMA support
The block diagram of the UARTAn is shown below.
Block diagram of Asynchronous Serial Interface UARTAn
For the configuration of the baud rate generator, see Figure 16-11 on
page 533.
UARTAn consists of the following hardware units.
Preliminary User’s Manual U17566EE1V2UM00
Receive shift
Interconnect Network) communication format
– Recognition of 11 bits or more possible for SBF reception in LIN
– SBF reception flag provided
Two different DMA trigger events in transmission mode (refer to “DMA
Controller (DMAC)“ on page 309)
Selector
UAnRX
register
Filter
communication format
UAnCTL1
UAnCTL2
Reception
controller
Reception unit
Baud rate
generator
UAnCTL0
Internal bus
Internal bus
UAnSTR
Asynchronous Serial Interface (UARTA)
Transmission unit
Transmission
controller
Baud rate
generator
UAnOTP0
shift register
Transmit
Selector
UAnTX
TXDAn
RXDAn
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