upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 352

• Manufacturer Part Number: upd70f3422gj-gae-qs-ax
• Description: 32-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

Chapter 11
352
Bit position
5
4
0
Initial Value
Table 11-8
Address
Caution
Access
TPnCCS1
TPnCCS0
Bit name
TPnOVF
(6)
TPnOPT0 - TMPn option register 0
The TPnOPT0 register is an 8-bit register used to set the capture/compare
operation and detect an overflow.
This register can be read/written in 8-bit or 1-bit units.
<base> + 5
00
TPnOPT0 register contents
1.
2.
Preliminary User’s Manual U17566EE1V2UM00
H
Rewrite the TPnCCS1 and TPnCCS0 bits when the TPnCE bit = 0. (The
same value can be written when the TPnCE bit = 1.) If rewriting was
mistakenly performed, clear the TPnCE bit to 0 and then set the bits again.
Be sure to clear bits 1 to 3, 6, and 7 to 0.
R/W
. This register is initialized by any reset.
7
0
Function
TPnCCR1 register capture/compare selection:
The TPnCCS1 bit setting is valid only in the free-running timer mode.
TPnCCR0 register capture/compare selection:
The TPnCCS0 bit setting is valid only in the free-running timer mode.
TMPn overflow detection flag:
• The TPnOVF bit is reset when the 16-bit counter count value overflows from
• An interrupt request signal (INTTPnOV) is generated at the same time that
• The TPnOVF bit is not cleared even when the TPnOVF bit or the TPnOPT0
• The TPnOVF bit can be both read and written, but the TPnOVF bit cannot be
0: compare register selected
1: capture register selected
0: compare register selected
1: capture register selected
Set (1):
Reset (0): TPnOVF bit 0 written or TPnCTL0.TPnCE bit = 0
FFFFH to 0000H in the free-running timer mode or the pulse width
measurement mode.
the TPnOVF bit is set to 1. The INTTPnOV signal is not generated in modes
other than the free-running timer mode and the pulse width measurement
mode.
register are read when the TPnOVF bit = 1.
set to 1 by software. Writing 1 has no influence on the operation of TMPn.
H
R/W
6
0
Overflow occurred
TPnCCS1 TPnCCS10
R/W
5
R/W
4
16-bit Timer/Event Counter P (TMP)
R/W
3
0
R/W
2
0
R/W
1
0
TPnOVF
R/W
0