upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 359
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upd70f3422gj-gae-qs-ax
Manufacturer Part Number
upd70f3422gj-gae-qs-ax
Description
32-bit Single-chip Microcontroller
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.UPD70F3422GJ-GAE-QS-AX.pdf
(930 pages)
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16-bit Timer/Event Counter P (TMP)
TPnCTL0
INTTPnCC0 signal
TPnCCR0 register
TOPn0 pin output
Figure 11-3
16-bit counter
TPnCE bit
TPnCE
0/1
FFFFH
0000H
(1)
Basic timing of operation in interval timer mode
When the TPnCE bit is set to 1, the value of the 16-bit counter is cleared from
FFFFH to 0000H in synchronization with the count clock, and the counter
starts counting. At this time, the output of the TOPn0 pin is inverted.
Additionally, the set value of the TPnCCR0 register is transferred to the CCR0
buffer register.
When the count value of the 16-bit counter matches the value of the CCR0
buffer register, the 16-bit counter is cleared to 0000H, the output of the TOPn0
pin is inverted, and a compare match interrupt request signal (INTTPnCC0) is
generated.
The interval can be calculated by the following expression.
Register setting for interval timer mode operation
(a) TMPn control register 0 (TPnCTL0)
Preliminary User’s Manual U17566EE1V2UM00
0
Interval = (Set value of TPnCCR0 register + 1) × Count clock cycle
Interval (D
0
D
0
0
+ 1) Interval (D
0
0
D
0
0
+ 1) Interval (D
TPnCKS2 TPnCKS1 TPnCKS0
D
0/1
0
D
0
0/1
0
+ 1) Interval (D
0/1
D
0
Select count clock
0: Stop counting
1: Enable counting
0
+ 1)
Chapter 11
359
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