upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 167

• Manufacturer Part Number: upd70f3422gj-gae-qs-ax
• Description: 32-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

Clock Generator
During power save
Wake-up signals
4.3.1 Power save modes description
mode
4.3 Power Save Modes
This chapter describes the various power save modes and how they are
operated. For details see:
• “Power save modes description” on page 167
• “Power save mode activation” on page 179
• “CPU operation after power save mode release” on page 181
This section explains the various power save modes in detail.
During all power save modes, the pins behave as follows:
• All output pins retain their function. That means all outputs are active,
• All input pins remain as input pins.
• All input pins with stand-by wake-up capability remain active, the function of
During all power save modes, the main and sub oscillator clock monitors
remain active, provided that the monitored oscillator is operating. If the
oscillator is switched off during stand-by, the associated clock monitor enters
stand-by as well.
The following signals can awake the controller from power save modes IDLE,
WATCH, Sub-WATCH, STOP:
• Reset signals
• Non maskable interrupts
• Maskable interrupts
Preliminary User’s Manual U17566EE1V2UM00
provided the required clock source is available.
all others is disabled.
– external RESET
– Power-On-Clear reset RESPOC
– Watchdog Timer reset RESWDT
– Clock monitors resets RESCMM, RESCMS
– NMI0
– NMIWDT
– external interrupts INTPn
– CAN wake up interrupts INTCnWUP
The Watchdog Timer must be configured to generate the reset WDTRES
in case of overflow (WDTM.WDTMODE = 1) and it’s input clock WDTCLK
must be active during stand-by.
The main oscillator respectively sub oscillator must be active during
stand-by.
The appropriate port must be configured correctly.
The Watchdog Timer must be configured to generate the in case of
overflow (WDTM.WDTMODE = 0) and it’s input clock WDTCLK must be
active during stand-by.
The appropriate port must be configured correctly.
The appropriate port and the CAN (CnCTRL.PSMODE[1:0] = 01
be configured correctly.
Chapter 4
B
) must
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