upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 236

• Manufacturer Part Number: upd70f3422gj-gae-qs-ax
• Description: 32-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

Chapter 6
236
6.2.2 Interrupt handling during flash self-programming
Note
This microcontroller provides functions to maintain interrupt servicing during
the self-programming procedure.
It is recommended to refer to the application note “Self-Programming”
(document nr. U16929EE) for comprehensive information concerning flash
self-programming, which explains also the functions of the self-programming
library. The latest version of this document can be loaded via the URL
Since neither the interrupt vector table nor the interrupt handler routines, which
are normally located in the flash memory, are accessible during self-
programming, interrupt acknowledges have to be re-routed to non-flash
memory, i.e. to the internal RAM or - for µPD70F3427 only - to the external
memory.
Therefore two prerequisites are necessary to enable interrupt servicing during
self-programming:
• The concerned interrupt handler routine needs to be copied to the internal
• The concerned interrupt acknowledge has to be re-routed to that handler.
The internal firmware and the self-programming library provide functions to
initialize and process such interrupts.
The interrupt handler routines can be copied from flash to the internal RAM,
respectively external memory, by use of the SelfLib_UsrIntToRam self-
programming library function.
The addresses of the interrupt handler routines are set up via the
SelfLib_RegisterInt self-programming library function.
1.
2.
All interrupt vectors are relocated to one entry point in the internal RAM:
• New entry point of all maskable interrupts is the 1st address of the internal
• New entry point of all non maskable interrupts is the word address following
In general a jump to a special handler routine will be placed at the 1st and 2nd
internal RAM address, which identifies the interrupt sources and branches to
the correct interrupt service routine.
The function serving the interrupt needs to be compiled as an interrupt function
(i.e. terminate with a RETI instruction, save/restore all used registers, etc.).
Preliminary User’s Manual U17566EE1V2UM00
RAM, respectively external memory.
RAM. A handler routine must check the interrupt source. The interrupt
request source can be identified via the interrupt/exception source register
ECR.EICC (refer to “System register set“ on page 107)
the maskable interrupt entry, i.e. the second address of the internal RAM.
The interrupt request source can be identified via the interrupt/exception
source register ECR.FECC (refer to“System register set“ on page 107).
http://www.ee.nec.de/updates
Note that this special interrupt handling adds some interrupt latency time.
Special interrupt handling is done only during the flash programming
environment is activated. If self-programming is deactivated, the normal
interrupt vector table in the flash memory is used.
Flash Memory