upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 775
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upd70f3422gj-gae-qs-ax
Manufacturer Part Number
upd70f3422gj-gae-qs-ax
Description
32-bit Single-chip Microcontroller
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.UPD70F3422GJ-GAE-QS-AX.pdf
(930 pages)
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A/D Converter (ADC)
a)
b)
c)
3
0
0
0
0
0
0
0
0
1
When A/D conversion is started by ADA0M0.ADA0CE = 0
delayed by the given stabilization time. This ensures compliance with the necessary stabilization time.
The stabilization time applies only prior to the first sampling.
The conversion time is calculated by (31 x div) / f
The sampling time is calculated by (16.5 x div) / f
ADA0FR
2
0
0
0
0
1
1
1
1
x
Table 20-2
1
0
0
1
1
0
0
1
1
x
0
0
1
0
1
0
1
0
1
x
Note
divider
div
1
2
3
4
5
6
7
8
Conversion time settings
Note that the given times in Table 20-2 do not regard the dithering of the A/D
converter supply clock. Using a dithering supply clock does not impact the A/D
converter’s operation.
Preliminary User’s Manual U17566EE1V2UM00
conversion
11.63 µs
13.56 µs
15.50 µs
3.88 µs
5.81 µs
7.75 µs
9.69 µs
time
b
f
SPCLK0
prohibited
= 16 MHz
sampling time
2.06 µs
3.09 µs
4.13 µs
5.16 µs
6.12 µs
7.22 µs
8.25 µs
SPCLK0.
SPCLK0.
c
prohibited
conversion
→
15.50 µs
7.75 µs
time
1 the first sampling of the ANIn input is
b
f
SPCLK0
prohibited
prohibited
prohibited
prohibited
prohibited
prohibited
= 4 MHz
sampling time
4.13 µs
8.25 µs
c
Stabilization
Chapter 20
16/f
31/f
47/f
50/f
50/f
50/f
50/f
50/f
time
SPCLK0
SPCLK0
SPCLK0
SPCLK0
SPCLK0
SPCLK0
SPCLK0
SPCLK0
a
775
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