upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 837

• Manufacturer Part Number: upd70f3422gj-gae-qs-ax
• Description: 32-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

LCD Bus Interface (LCD-I/F)
LBCTL0.BYF0
LBCTL0.TPF0
DBWR(R/W)
DBRD(E)
DBRD(E)
LBDATA0
LBCTL.EL=1
LBCTL.EL=0
DBD[7:0]
INTLCD
write buffer
SPCLK
internal
Figure 23-5
Sequence
Note
write 1st byte to LBDATA0 register
(3)
Writing bytes
Writing consecutive bytes transmits these bytes to the external LCD controller/
driver.
Timing (mod68 mode: LBTCTL0.IMD0 = 1): write consecutive bytes,
LBWST0.WST0 = 5, LBCYC0.CYC0 = 8, , LBCTL0.TCIS0 = 0
The timing diagrams are for functional explanation purposes only without any
relevance to the real hardware implementation.
1. The first byte of LCD data is written to the LBDATA0 register. The internal
2. The LBDATA0 register contents is copied to the write buffer. This clears
3. Caused by the interrupt, the DMA writes a second byte to LBDATA0. The
4. Since the transfer (one byte) on the external bus interface is still going on
5. After the transfer on the external bus interface has been completed, the
Filling the write buffer starts a new transfer to the external LCD controller.
Preliminary User’s Manual U17566EE1V2UM00
1st byte
bus transfer takes some clocks until the register of the interface is written.
Then the busy flag LBCTL0.BYF0 is set until the data is copied to the write
buffer.
LBCTL0.BYF0 and causes the interrupt output to become active for one
clock cycle. Transfer on the external bus interface is started. The flag
LBCTL0.TPF0 is set to indicate that a transfer is in progress.
CPU can write this byte as well after it has checked the busy flag
LBCTL0.BYF0. The internal bus transfer again takes some clock cycles
until the LBDATA0 register is written and LBCTL0.BYF0 is set.
and the LBDATA0 register contents can not be copied to the write buffer
immediately, the busy flag LBCTL0.BYF0 remains set.
write buffer is filled with the contents of LBDATA0. The busy flag
LBCTL0.BYF0 is cleared and the interrupt output INTLCD becomes active
for one clock cycle.
write 2nd byte to LBDATA0 register
1st byte
1st byte
2nd byte
write 3rd byte to LBDATA0 register
2nd byte
2nd byte
3rd byte
3rd byte
3rd byte
Chapter 23
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