upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 326

• Manufacturer Part Number: upd70f3422gj-gae-qs-ax
• Description: 32-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

Chapter 8
326
DMA Transfer
DMA Transfer
Request CH3
Request CH2
EN0 bit of DCHC0 register
Figure 8-2
Figure 8-3
Caution
8.10 Forcible Termination
CPU
EN2 bit = 1
TC2 bit = 0
DSAL2, DSAH2,
DDAL2, DDAH2
CPU
NMI (input)
Example of forcible interruption of DMA transfer
The resumed DMA transfer after NMI interruption cannot be executed with new
settings. New settings for a DMA transfer can be validated either after the end
of the current transfer or after the transfer has been forcibly terminated by
setting the INITn bit of the DCHCn register.
In addition to the forcible interruption operation by means of the NMI input,
DMA transfer can be forcibly terminated by the INITn bit of the DCHCn register.
The following is an example of the operation of a forcible termination.
Figure 8-3 shows a block transfer of channel 3 which begins during the DMA
block transfer of DMA channel 2. The block transfer of DMA channel 2 is
forcibly terminated by setting the INIT2 bit of its DCHC2 control register.
DMA transfer forcible termination example 1
Preliminary User’s Manual U17566EE1V2UM00
CPU
Set register
DSAL3, DSAH3,
DDAL3, DDAH3
EN3 bit = 1
TC3 bit = 0
CPU DMA2
DMA transfer
Set register
DMA2
DMA transfer stop
DMA2
Forcible
interruption
DMA2 DMA2
DCHC2
(INIT2 bit = 1)
DMA channel 2 transfer is forcibly terminated
and the bus is released
Set register
EN2 bit
TC2 bit = 0
DMA transfer
Transfer
restart
CPU
DMA channel 3 transfer begins
DMA3
→
0
DMA3
DMA channel 3 terminal count
DMA3 DMA3 CPU
DMA transfer stop
Forcible
interruption
DMA Controller (DMAC)
EN3 bit
TC3 bit
CPU
→
→
1
0
CPU