upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 828

• Manufacturer Part Number: upd70f3422gj-gae-qs-ax
• Description: 32-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

Chapter 23
828
Bit position
5 to 4
7
6
3
1
0
Initial Value
Table 23-4
Address
Access
LBC0[1:0]
Bit name
TCIS0
BYF0
IMD0
TPF0
EL0
(1)
LBCTL0 - LCD Bus Interface control register
The 8-bit LBCTL0 register controls the operation of the LCD Bus Interface.
This register can be read/written in 8-bit or 1-bit units.
FFFF FB60
00
LBCTL0 register contents
Preliminary User’s Manual U17566EE1V2UM00
H
Function
Level of signal “E” in mod68 mode
Mode of external bus interface access
Selects the internal clock
Select interrupt generation
Transfer in progress on external bus interface
Data register busy
R/W
EL0
. This register is cleared by any reset.
0: E is active high; data is read/written on the falling edge.
1: E is active low, data is read/written on the rising edge.
0: mod80 mode - control signals are WR and RD
1: mod68 mode - control signals are E and R/W
0: During write access to the bus interface, an interrupt is generated as soon as
1: An interrupt is generated as soon as the read or write transfer via the bus
0: The external bus interface is idle
1: Data is transferred on the external bus interface
0: Data can be read or written from/to LBDATA0
1: Register LBDATA0 (LBDATAR0) is busy
7
LBC01
data is transferred from LBDATA0 to the write buffer.
During read access from the bus interface, an interrupt is generated as soon as
data is available in the LBDATA0 and LBDATAR0 registers.
interface has completed.
Data can be read from LBDATAR0
0
0
1
1
H
IMD0
R/W
6
LBC00
0
1
0
1
LBC01
R/W
5
Selected clock
SPCLK0
SPCLK1
SPCLK2
SPCLK5
LBC00
R/W
4
TCIS0
R/W
3
LCD Bus Interface (LCD-I/F)
R
2
0
TPF0
R
1
BYF0
R
0