upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 662

• Manufacturer Part Number: upd70f3422gj-gae-qs-ax
• Description: 32-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

Chapter 19
662
Segment name
Time segment 1 (TSEG1)
Time segment 2 (TSEG2)
reSynchronization Jump
Width (SJW)
Figure 19-18
Table 19-15
19.3.7 Baud rate control function
Note
Sync segment
(1)
(2)
Prescaler
The CAN Controller has a prescaler that divides the clock (f
CAN. This prescaler generates a CAN protocol layer base clock (f
CAN module system clock (f
module bit rate prescaler register“ on page 693).
Data bit time (8 to 25 time quanta)
One data bit time is defined as follows.
The CAN Controller sets time segment 1, time segment 2, and
reSynchronization Jump Width (SJW) as the data bit time, as shown in
Figure 19-18
segment and phase segment 1 that are defined by the CAN protocol
specification. Time segment 2 is equivalent to phase segment 2.
Segment setting
Segment setting
1.
2.
Preliminary User’s Manual U17566EE1V2UM00
1 time quantum = 1/f
IPT: Information Processing Time
Reference: The CAN protocol specification defines the segments
constituting the data bit time as shown in
Settable range
2TQ to 15TQ
1TQ to 8TQ
1TQ to 4TQ
Prop segment
. Time segment 1 is equivalent to the total of the propagation (prop)
Time segment 1(TSEG1)
Data bit time(DBT)
TQ
Phase segment 1
CANMOD
Notes on setting to conform to CAN
specification
-
IPT
to the CAN protocol specification, therefore, a
length equal to phase segment 1 must be set here.
This means that the length of time segment 1
minus 1TQ is the settable upper limit of time
segment 2.
The settable upper limit of SJW is the length of
time segment 1 minus 1TQ.
) divided by 1 to 256 (“CnBRP - CANn
Note
Sample point (SPT)
of the CAN Controller is 0TQ. To conform
Figure 19-19
Phase segment 2
Time segment 2
(TSEG2)
CAN Controller (CAN)
.
SJW
CAN
) supplied to
TQ
) that is the