upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 522

• Manufacturer Part Number: upd70f3422gj-gae-qs-ax
• Description: 32-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

Chapter 16
522
Sleep
bus
TXDAn (output)
Edge detection
Figure 16-3
Reception interrupt (INTUAnR)
Capture timer
Disable
Note
Wake-up
signal
frame
Enable
4.
LIN reception manipulation outline
1.
2.
3.
4.
5.
Preliminary User’s Manual U17566EE1V2UM00
Note 1
A transmission enable interrupt request signal (INTUAnT) is output at the
start of each transmission. The INTUAnT signal is also output at the start
of each SBF transmission.
The wakeup signal is sent by the pin edge detector, UARTAn is enabled,
and the SBF reception mode is set.
The receive operation is performed until detection of the stop bit. Upon
detection of SBF reception of 11 or more bits, normal SBF reception end is
judged, and an interrupt signal is output. Upon detection of SBF reception
of less than 11 bits, an SBF reception error is judged, no interrupt signal is
output, and the mode returns to the SBF reception mode.
If SBF reception ends normally, an interrupt request signal is output. The
timer is enabled by an SBF reception complete interrupt. Moreover, error
detection for the UAnSTR.UAnOVE, UAnSTR.UAnPE, and
UAnSTR.UAnFE bits is suppressed and UART communication error
detection processing and UARTAn receive shift register and data transfer
of the UAnRX register are not performed. The UARTAn receive shift
register holds the initial value, FFH.
The RXDAn pin is connected to TI (capture input) of the timer, the transfer
rate is calculated, and the baud rate error is calculated. The value of the
UAnCTL2 register obtained by correcting the baud rate error after dropping
UARTA enable is set again, causing the status to become the reception
status.
Check-sum field distinctions are made by software. UARTAn is initialized
following CSF reception, and the processing for setting the SBF reception
mode again is performed by software.
Disable
reception
Note 2
13 bits
Synch
break
SBF
field
Note 3
Enable
SF reception
Synch
field
Note 4
ID reception
Asynchronous Serial Interface (UARTA)
Ident
field
transmission
Data
DATA
field
transmission
Data
DATA
field
Data transmission
Check
Note 5
SUM
field