upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 500

• Manufacturer Part Number: upd70f3422gj-gae-qs-ax
• Description: 32-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

Chapter 15
500
SYSRESWDT
SYSRES
15.1.4 Reset behavior
Note
The reset of the Watchdog Timer is controlled by the two reset inputs SYSRES
and SYSRESWDT. The respective signals are generated by the Reset module.
Every reset sets the WDCS register to the longest possible running time.
The watchdog reset SYSRESWDT is used to initialize the Watchdog Timer.
This signal is generated at power-on and after external RESET.
After SYSRESWDT, all registers are set to their reset values, and the timer is
stopped. You have to write the required settings to the WDCS register and may
start the counter. Once the counter has been started, it cannot be
reprogrammed or stopped unless the next reset (SYSRES or SYSRESWDT)
occurs.
SYSRES is generated by all reset sources.
SYSRES does not reset the register WDTM. That means, the timer status
(running or stopped) and mode (generate interrupt or reset request) remain
unchanged.
If the Watchdog Timer was running before SYSRES was released, the counter
is automatically cleared and restarts with the new timing.
1.
2.
Preliminary User’s Manual U17566EE1V2UM00
Every reset clears also the WCC register. That means, the WDTCLK has
the frequency of the 240 KHz ring oscillator. In combination with the largest
time factor (2
After any reset, the write protection for WDCS is disabled. WDCS can be
written once to specify a shorter time interval. After that, the WDCS
register is write-protected.
20
), this yields a running time of 4.37 s.
Watchdog Timer (WDT)