upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 834

• Manufacturer Part Number: upd70f3422gj-gae-qs-ax
• Description: 32-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

Chapter 23
834
DBD[7:0]
DBD[7:0]
(WRITE)
interrupt
DBWR
DBRD
(READ)
Internal
(TCIS=0)
(TCIS=1)
Figure 23-2
23.3.1 Timing dependencies
23.3 Timing
Note
on write
Read or write byte from/to LBDATA register by CPU or DMA
This section starts with the general timing and then presents examples of
consecutive write and read operations.
The following figure shows the general timing when the mod80 mode is used.
It illustrates the effect of the LBCYC0 and LBWST0 register settings. It explains
also the impact of LBCTL0.TCIS on the interrupt generation.
LCD Bus Interface timing (mod80 mode)
In mod80 mode, DBWR provides the write strobe WR and DBRD the read
strobe RD.
1.
2.
3.
The only difference in mod68 mode is, that DBWR provides the read/write R/W
strobe and DBRD the E strobe. The active edge of the E strobe is defined by
LBCTL0.EL0.
Preliminary User’s Manual U17566EE1V2UM00
T is the clock period of the selected SPCLK.
CYC is the chosen number of clock cycles (LBCYC0.CYC0). Always keep
LBCYC0.CYC0 > 2.
WST is the chosen number of wait states (LBWST0). Always keep
LBWST0.SWST0 < (LBCYC0.CYC0 – 2).
(WST+1) * T
Data
CYC * T
Data
on read
LCD Bus Interface (LCD-I/F)
next byte