upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 550

• Manufacturer Part Number: upd70f3422gj-gae-qs-ax
• Description: 32-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

Chapter 17
550
Bit position
7
0
Initial Value
Table 17-7
Address
Access
Bit name
CBnOVE
Note
CBnTSF
(4)
CBnSTR - CSIBn status register
CBnSTR is an 8-bit register that displays the CSIBn status.
This register can be read/written in 8-bit or 1-bit units.
Bit CBnTSF is read-only.
<base> + 3
00
In addition to reset input, the CBnSTR register can be initialized by clearing the
CBnCTL0.CBnPWR bit to 0.
CBnSTR register contents
In case of an overrun error, the reception error interrupt INTCBnRE behaves
different, depending on the transfer mode:
• Continuous transfer mode
• Single transfer mode
In either case the overflow flag CBnSTR.CBnOVE is set to 1 and the previous
data in CBnRX will be overwritten with the new data.
Preliminary User’s Manual U17566EE1V2UM00
CBnTSF
H
The reception error interrupt INTCBnRE is generated instead of the
reception completion interrupt INTCBnR.
No interrupt is generated.
. This register is cleared by any reset.
R
7
Function
Communication status flag
During transmission, this register is set when data is prepared in the CBnTX
register, and during reception, it is set when a dummy read of the CBnRX register
is performed.
When transfer ends, this flag is cleared to 0 at the last edge of the clock.
Overrun error flag
• An overrun error occurs when the next reception starts without performing a
• The CBnOVE flag is cleared by writing 0 to it. It cannot be set even by writing
0: Communication stopped
1: Communicating
0: No overrrun
1: Overrun
CPU read of the value of the receive buffer, upon completion of the receive
operation.
The CBnOVE flag displays the overrun error occurrence status in this case.
1 to it.
H
R/W
6
0
R/W
5
0
R/W
4
0
R/W
3
0
Clocked Serial Interface (CSIB)
R/W
2
0
R/W
1
0
CBnOVE
R/W
0