upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 890
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upd70f3422gj-gae-qs-ax
Manufacturer Part Number
upd70f3422gj-gae-qs-ax
Description
32-bit Single-chip Microcontroller
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.UPD70F3422GJ-GAE-QS-AX.pdf
(930 pages)
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Chapter 28
890
28.5 Restrictions and Cautions on On-Chip Debug
Function
• Do not mount a device that was used for debugging on a mass-produced
• If a reset signal (reset input from the target system or reset by an internal
• Even if reset is masked by using a mask function, the I/O buffer (port pin,
• With a debugger that can set software breakpoints in the internal flash
• The RESET signal input is masked during a break.
• The POC reset operation cannot be emulated.
• The on-chip debugging unit uses the exception vector address 60
Preliminary User’s Manual U17566EE1V2UM00
product (this is because the flash memory was rewritten during debugging
and the number of rewrites of the flash memory cannot be guaranteed).
reset source) is input during RUN (program execution), the break function
may malfunction.
etc.) is reset when a pin reset signal is input.
memory, the breakpoints temporarily become invalid when pin reset or
internal reset is effected. The breakpoints become valid again if a break
such as a hardware break or forced break is executed. Until then, no
software break occurs.
software breakpoint (DBTRAP, refer to “Interrupt Controller (INTC)” on
page 187). Thus the debugger takes over control when one of the following
exceptions occur:
– debug trap (DBTRAP)
– illegal op-code detection (ILGOP)
– ROM Correction
The debugger executes its own exception handler. Therefore, the user's
exception handler at address 60
H
will not be executed.
On-Chip Debug Unit
H
for
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