upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 867

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upd70f3422gj-gae-qs-ax

Manufacturer Part Number
upd70f3422gj-gae-qs-ax
Description
32-bit Single-chip Microcontroller
Manufacturer
Renesas Electronics Corporation.
Datasheet
Reset
Table 26-3
26.1.4 Reset by Watchdog Timer
26.1.5 Reset by Clock Monitor
26.2 Reset Registers
The Watchdog Timer can be configured to generate a reset if the watchdog
time expires. After watchdog reset, the RESSTAT.RESWDT bit is set. The
system reset signal SYSRES is generated.
After Watchdog Timer overflow, the reset status lasts for a specific time. Then
the reset status is automatically released.
The two Clock Monitors generate a reset when either the main oscillator or the
sub-oscillator fails. After a Clock Monitor reset, the corresponding bit
(RESSTAT.RESCMM or RESSTAT.RESCMS) is set. The system reset signal
SYSRES is generated.
After a Clock Monitor reset, the reset status lasts for a specific time. Then the
reset status is automatically released.
The reset functions are controlled and operated by means of the following
registers:
Reset function registers overview
Preliminary User’s Manual U17566EE1V2UM00
Register name
Reset source flag register
Shortcut
RESSTAT
Address
FFFF FF20
Chapter 26
H
867

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