upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 577

• Manufacturer Part Number: upd70f3422gj-gae-qs-ax
• Description: 32-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

I
2
C Bus (IIC)
(10)
(11)
(12)
(13)
(5)
(6)
(7)
(8)
(9)
Prescaler
This selects the sampling clock to be used.
Serial clock counter
This counter counts the serial clocks that are output and the serial clocks that
are input during transmit/receive operations and is used to verify that 8-bit data
was transmitted or received.
Interrupt request signal generator
This circuit controls the generation of interrupt request signals (INTIICn).
An I
• Falling edge of eighth or ninth clock of the serial clock (set by IICCn.WTIMn
• Interrupt occurrence due to stop condition detection (set by IICCn.SPIEn bit)
Serial clock controller
In master mode, this circuit generates the clock output via the SCLn pin from
the sampling clock.
Serial clock wait controller
This circuit controls the wait timing.
ACK output circuit, stop condition detector, start condition detector, and
ACK detector
These circuits are used to output and detect various control signals.
Data hold time correction circuit
This circuit generates the hold time for data corresponding to the falling edge
of the SCLn pin.
Start condition generator
A start condition is issued when the IICCn.STTn bit is set.
However, in the communication reservation disabled status
(IICFn.IICRSVn = 1), this request is ignored and the IICFn.STCFn bit is set if
the bus is not released (IICFn.IICBSYn = 1).
Bus status detector
Whether the bus is released or not is ascertained by detecting a start condition
and stop condition.
However, the bus status cannot be detected immediately after operation, so
set the bus status detector to the initial status by using the IICFn.STCENn bit.
Preliminary User’s Manual U17566EE1V2UM00
bit)
2
C interrupt is generated following either of two triggers:
Chapter 18
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