upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 663
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upd70f3422gj-gae-qs-ax
Manufacturer Part Number
upd70f3422gj-gae-qs-ax
Description
32-bit Single-chip Microcontroller
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.UPD70F3422GJ-GAE-QS-AX.pdf
(930 pages)
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CAN Controller (CAN)
Segment name
Sync segment
(Synchronization segment)
Prop segment
(Propagation segment)
Phase segment 1
(Phase buffer segment 1)
Phase segment 2
(Phase buffer segment 2)
SJW
(reSynchronization Jump
Width)
Figure 19-19
Table 19-16
Note
Sync segment
Configuration of data bit time defined by CAN specification
Configuration of data bit time defined by CAN specification
1.
Preliminary User’s Manual U17566EE1V2UM00
IPT: Information Processing Time
Settable range
1
Programmable to 1 to 8
Programmable to 1 to 8
Phase segment 1 or
IPT
Programmable from 1 to
phase segment 1 to 4,
whichever is smaller
Note
Prop segment
, whichever greater
Data bit time(DBT)
Phase segment 1
Notes on setting to conform to CAN
specification
This segment starts at the edge where the level
changes from recessive to dominant when
hardware synchronization is established.
This segment absorbs the delay of the output
buffer, CAN bus, and input buffer.
The length of this segment is set so that ACK is
returned before the start of phase segment 1.
Time of prop segment ≥ (Delay of output buffer) +
2 × (Delay of CAN bus) + (Delay of input buffer)
This segment compensates for an error in the data
bit time. The longer this segment, the wider the
permissible range but the slower the
communication speed.
This width sets the upper limit of expansion or
contraction of the phase segment during
resynchronization.
Sample point (SPT)
Phase segment 2
SJW
Chapter 19
663
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