upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 467

• Manufacturer Part Number: upd70f3422gj-gae-qs-ax
• Description: 32-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

16-bit Multi-Purpose Timer G (TMG)
Caution
Setting Method:
(1)
(2)
(3)
(4)
(5)
(6)
(7)
Operation of PWM (match and clear):
(1)
Do not set 0000H in GCCn0 or GCCn5 in match and clear modus.
(2)
(3)
(4)
(5)
(6)
Preliminary User’s Manual U17566EE1V2UM00
An usable compare register is one of GCCn1 to GCCn4, and the
corresponding counters TMGn0 or TMGn1 must be selected with the
TBGnm bit (m = 1 to 4).
Select a count clock cycle with the CSE12 to CSE10 (TMGn1) bits or
CSE02 to CSE00 (TMGn0) bits.
Specify the active level of a timer output (TOGnm) with the ALVGnm bit.
When using multiple timer outputs, the user can prevent TOGnm from
making transitions simultaneously by setting the OLDEn bit of TMGMHn
register. (This capability is useful for reducing noise and current.)
Set an upper limit on the value of the counter in GCCn0 or GCCn5.
(Timer Dn 0000H is forbidden)
Write data to GCCnm.
Start count operation by setting POWERn bit and TMGn0E bit (or
TMGn1E bit).
When the value of the counter matches the value of GCCnm, a match
interrupt (INTCCGnm) is output.
When the value of GCCn0 (GCCn5) matches the value of the counter,
INTCCGn0 (INTCCGn5) is output, and the counter is cleared. This
operation is referred to as "match and clear".
TOGnm does not make a transition until the first match and clear event.
TOGnm makes a transition to the active level after the first match and
clear event.
When the value of the counter matches the value of GCCnm, TOGnm
makes a transition to the inactive level, and a match interrupt
(INTCCGnm) is output.
When the next match and clear event occurs, INTCCGn0 (INTCCGn5) is
output, and the counter is cleared. The counter resumes count-up
operation starting with 0000H.
Chapter 13
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