upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 420

• Manufacturer Part Number: upd70f3422gj-gae-qs-ax
• Description: 32-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

Chapter 11
420
input/capture
trigger input)
trigger input)
event count
Figure 11-37
TIPn0 pin
TIPn1 pin
(external
(capture
Internal count clock
11.5.7 Pulse width measurement mode (TPnMD2 to TPnMD0 = 110)
detector
detector
detector
Edge
Edge
Edge
In the pulse width measurement mode, 16-bit timer/event counter P starts
counting when the TPnCTL0.TPnCE bit is set to 1. Each time the valid edge
input to the TIPnm pin has been detected, the count value of the 16-bit counter
is stored in the TPnCCRm register, and the 16-bit counter is cleared to 0000H.
The interval of the valid edge can be measured by reading the TPnCCRm
register after a capture interrupt request signal (INTTPnCCm) occurs.
Select either the TIPn0 or TIPn1 pin as the capture trigger input pin. Specify
“No edge detected” by using the TPnIOC1 register for the unused pins.
When an external clock is used as the count clock, measure the pulse width of
the TIPn1 pin because the external clock is fixed to the TIPn0 pin. At this time,
clear the TPnIOC1.TPnIS1 and TPnIOC1.TPnIS0 bits to 00 (capture trigger
input (TIPn0 pin): No edge detected).
Configuration in pulse width measurement mode
Preliminary User’s Manual U17566EE1V2UM00
selection
TPnCE bit
Count
clock
TPnCCR0 register
(capture)
TPnCCR1 register
Clear
16-bit counter
(capture)
16-bit Timer/Event Counter P (TMP)
INTTPnOV
INTTPnCC0
INTTPnCC1
signal
signal
signal