upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 866

• Manufacturer Part Number: upd70f3422gj-gae-qs-ax
• Description: 32-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

Chapter 26
866
Internal system
Main oscillator
Ring oscillator
reset signal
Figure 26-3
CPU clock
RESET
26.1.3 External RESET
(eliminated as noise)
Note
Analog delay
Reset is performed when a low level signal is applied to the RESET pin.
The reset status is released when the signal applied to the RESET pin
changes from low to high.
After the external RESET is released, the RESSTAT register is cleared and the
RESSTAT.RESEXT bit is set (RESSTAT = 02
source flag register“ on page 868 for the interaction between Power-On-Clear
and external RESET). The system reset signals SYSRES and SYSRESWDT
are generated.
The RESET pin incorporates a noise eliminator, which is applied to the reset
signal RESET. To prevent erroneous external reset due to noise, it uses an
analog filter. Even if no clock is active in the controller the external RESET can
keep the controller in reset state.
The internal system reset signals SYSRES and SYSRESWDT keep their
active level for at least four system clock cycles after the RESET pin is
released.
The following figure shows the timing when an external reset is performed. It
explains the effect of the noise eliminator. The noise eliminator uses the analog
delay to prevent the generation of an external reset due to noise.
The analog delay is caused by the analog input filter. The filter regards pulses
up to a certain width as noise and suppresses them. For the minimum RESET
pulse width refer to the Electrical Target Specification.
Timing for external RESET
Preliminary User’s Manual U17566EE1V2UM00
Analog
delay
Analog
delay
min. 4 ring oscillator clock cycles
H
, refer also to “RESSTAT - Reset
Reset