upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 785
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upd70f3422gj-gae-qs-ax
Manufacturer Part Number
upd70f3422gj-gae-qs-ax
Description
32-bit Single-chip Microcontroller
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.UPD70F3422GJ-GAE-QS-AX.pdf
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A/D Converter (ADC)
conversion
ADCR0n
INTAD
ANIn
Figure 20-6
A/D
20.4.4 Power-fail compare mode
(1)
The A/D conversion end interrupt request signal (INTAD) can be controlled as
follows by the ADA0PFM and ADA0PFT registers.
• If the power-fail compare mode is disabled (ADA0PFM.ADA0PFE = 0), the
• If the power-fail compare mode is enabled (ADA0PFM.ADA0PFE = 1) and
• If the power-fail compare mode is enabled (ADA0PFM.ADA0PFE = 1) and
In the power-fail compare mode, two modes are available as modes in which to
set the ANIn pins: continuous select mode and continuous scan mode.
Continuous select mode
In this mode, the higher 8 bits of conversion result of the ANIn channel in
ADA0CR0Hn, specified by ADA0S, is compared with the value of the
ADA0PFT register.
If the result of power-fail comparison matches the condition set by the
ADA0PFM.ADA0PFC bit, INTAD is generated.
In any case the next conversion is started.
Timing example of continuous select mode operation whit power-fail
comparison
Preliminary User’s Manual U17566EE1V2UM00
Data 1
INTAD signal is generated each time conversion is completed.
ADA0PFM.ADA0PFC = 0, the value of the ADCR0Hn register is compared
with the value of the ADA0PFT register when conversion is completed, and
the INTAD signal is generated only if ADCR0H0 ≥ ADA0PFT.
ADA0PFM.ADA0PFC = 1, the value of the ADCR0Hn register is compared
with the value of the ADA0PFT register when conversion is completed, and
the INTAD signal is generated only if ADCR0H0 < ADA0PFT.
ADA0PFT
unmatch
Data 1
Data 2
ADA0PFT
unmatch
Data 2
Data 3
ADA0PFT
match
Data 3
Data 4
ADA0PFT
match
Data 4
Data 5
ADA0PFT
unmatch
Data 5
Data 6
ADA0PFT
match
Chapter 20
785
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