upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 554

• Manufacturer Part Number: upd70f3422gj-gae-qs-ax
• Description: 32-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

Chapter 17
554
INTCBnR
CBnSCE
register
CBnTSF
CBnRX
SCKBn
SOBn
Shift
SIBn
17.4.2 Single transfer mode (master mode, reception mode)
CBnRX read (55H)
Note
(1)
(2)
(3)
(4)
(5)
L
MSB first (CBnCTL0.CBnDIR bit = 0), communication type 1 (see 16.4 (2)
CSIBn control register 1 (CBnCTL1), transfer data length = 8 bits
(CBnCTL2.CBnCL3 to CBnCTL2.CBnCL0 bits = 0, 0, 0, 0)
(1) Clear the CBnCTL0.CBnPWR bit to 0.
(2) Set the CBnCTL1 and CBnCTL2 registers to specify the transfer mode.
(3) Set the CBnCTL0.CBnRXE and CBnCTL0.CBnSCE bits to 1,
(4) Set the CBnPWR bit to 1 to enable the CSIBn operation.
(5) Perform a dummy read of the CBnRX register (reception start trigger).
(6) The reception complete interrupt request signal (INTCBnR) is output.
(7) Set the CBnSCE bit to 0 to set the final receive data status.
(8) Read the CBnRX register.
(9) Check that the CBnSTR.CBnTSF bit = 0 and set the CBnPWR bit to 0 to
To continue transfer, repeat steps (5) and (6) before (7). (At this time, (5) is not
a dummy read, but a receive data read combined with the reception trigger.)
The processing of steps (3) and (4) can be set simultaneously.
Preliminary User’s Manual U17566EE1V2UM00
55H (receive data)
CBnCTL0.TXE to 0, at the same time as specifying the transfer mode
using the CBnDIR bit, to set the reception enabled status.
stop the CSIBn operation (end of reception).
1
ABH
0
56H
1
ADH
0
5AH
1
B5H
0
Clocked Serial Interface (CSIB)
6AH
1
D5H
(6)
0
(AAH)
CBnRX read (AAH)
(7)
AAH
AAH
(8)
(9)
00H
00H