upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 584

• Manufacturer Part Number: upd70f3422gj-gae-qs-ax
• Description: 32-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

Chapter 18
584
Condition for clearing (COIn = 0)
• When a start condition is detected
• When a stop condition is detected
• Cleared by LRELn bit = 1 (communication save)
• When the IICEn bit changes from 1 to (operation
• After reset
Condition for clearing (TRCn = 0)
• When a stop condition is detected
• Cleared by LRELn = 1 (communication save)
• When the IICEn bit changes from 1 to 0 (operation
• Cleared by WRELn = 1
• When the ALDn bit changes from 0 to 1 (arbitration
• After reset
Master
• When “1” is output to the first byte’s LSB
Slave
• When a start condition is detected
When not used for communication
Condition for clearing (ACKDn = 0)
• When a stop condition is detected
• At the rising edge of the next byte’s first clock
• Cleared by LRELn = 1 (communication save)
• When the IICEn bit changes from 1 to 0 (operation
• After reset
ACKDn
stop)
TRCn
stop)
loss)
(transfer direction specification bit)
stop)
COIn
0
1
0
1
0
1
Addresses do not match.
Addresses match.
Receive status (other than transmit status). The SDAn line is set to high impedance.
Transmit status. The value in the SO latch is enabled for output to the SDAn line (valid starting at
the falling edge of the first byte’s ninth clock).
ACK was not detected.
ACK was detected.
Note
Note
The TRCn bit is cleared and SDAn line becomes high impedance when the
WRELn bit is set and the wait state is canceled at the ninth clock by
TRCn = 1.
Preliminary User’s Manual U17566EE1V2UM00
Transmit/receive status detection
Matching address detection
ACK detection
Condition for setting (COIn = 1)
•
Condition for setting (TRCn = 1)
Master
• When a start condition is generated
Slave
• When “1” is input by the first byte’s LSB
Condition for setting (ACKD = 1)
• After the SDAn bit is set to low level at the rising
address (SVAn register) (set at the rising edge of
the eighth clock).
(transfer direction specification bit)
edge of the SCLn pin’s ninth clock
When the received address matches the local
I
2
C Bus (IIC)