upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 319

• Manufacturer Part Number: upd70f3422gj-gae-qs-ax
• Description: 32-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

DMA Controller (DMAC)
Bit position
DCHC0
DCHC1
DCHC2
DCHC3
7
3
2
1
0
TC0
TC1
TC2
TC3
7
7
7
7
Bit name
8.3.5 DCHCn - DMA channel control registers
MLEn
STGn
INITn
TCn
ENn
6
0
6
0
6
0
6
0
These 8-bit registers are used to control the DMA transfer operating mode for
DMA channel n.
These registers can be read/written in 8-bit or 1-bit units. (However, bit 7 is
read only and bits 2 and 1 are write only. If bits 2 and 1 are read, the read
value is always 0.)
Preliminary User’s Manual U17566EE1V2UM00
Function
The Terminal Count status bit TC indicates whether DMA transfer through DMA
channel n has ended or not. It is read-only, and is set to 1 when DMA transfer ends
and cleared (0) when it is read.
When the Multi Link Enable bit MLE is set to 1 at terminal count output, the ENn bit
is not cleared to 0 and the DMA transfer enable state is retained (refer to
“Automatic Restart Function” on page 323). Moreover, the next DMA transfer
request can be accepted even when the TCn bit is not read, that means it is not
cleared.
When this bit is cleared to 0 at terminal count output, the ENn bit is cleared to 0 and
the DMA transfer disable state is entered. At the next DMA request, the setting of
the ENn bit to 1 and the reading of the TCn bit are required.
When this bit is set to 1, DMA transfer is forcibly terminated.
If this bit is set to 1 in the DMA transfer enable state (TCn bit = 0, ENn bit = 1),
DMA transfer is started.
Specifies whether DMA transfer through DMA channel n is to be enabled or
disabled.
If MLEn=0, this bit is cleared to 0 when DMA transfer ends.
If MLEn=1, this bit is not cleared and the next DMA transfer is automatically
restarted (refer to “Automatic Restart Function” on page 323).
This bit is also cleared to 0 when DMA transfer is forcibly terminated by means of
setting the INITn bit to 1 or by NMI input.
1: DMA transfer enabled
0: DMA transfer had not ended.
1: DMA transfer had ended.
0: DMA transfer disabled
5
0
5
0
5
0
5
0
4
0
4
0
4
0
4
0
MLE0
MLE1
MLE
MLE
3
3
3
3
INIT0
INIT1
INIT
INIT
2
2
2
2
STG0
STG1
STG
STG
1
1
1
1
EN0
EN1
EN2
EN3
0
0
0
0
FFFFF0E0H
FFFFF0E2H
FFFFF0E4H
FFFFF0E6H
Address
Address
Address
Address
Chapter 8
value
value
value
value
Initial
Initial
Initial
Initial
00H
00H
00H
00H
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