upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 498

• Manufacturer Part Number: upd70f3422gj-gae-qs-ax
• Description: 32-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

Chapter 15
498
WDTCLK
SYSRESWDT
SYSRES
Figure 15-1
15.1.1 Description
15.1.2 Principle of operation
(1)
Counter/Timer
clear
reset
The following figure shows a simplified block diagram.
Block diagram of the Watchdog Timer
As shown in the figure, the WDCS register controls the running time and the
WDTM register the operating mode.
The running time can be chosen between 2
Watchdog Timer clock WDTCLK.
The figure shows also, that the run and mode settings of the WDTM register
are only cleared by SYSRESWDT.
Before the Watchdog Timer is started, its running time and mode have to be
configured.
The Watchdog Timer has two operating modes:
• Mode 0 (generate non-maskable interrupt NMIWDT)
• Mode 1 (generate reset request RESWDT)
The mode is defined by the bit WDTM.WDTMODE. The mode can only be
changed after SYSRESWDT, that means, after external RESET or Power-On
Clear.
Watchdog Timer mode 0 (generate non-maskable interrupt NMIWDT)
If WDTM.WDTMODE is 0, the Watchdog Timer is in interrupt-request mode.
This is the default after initialization.
Setting bit WDTM.RUN to 1 starts the counter. Without intervention, the timer
will now run until the specified time has elapsed and then generate the non-
maskable interrupt NMIWDT. After that, the counter is reset to zero and starts
counting again.
Preliminary User’s Manual U17566EE1V2UM00
WDCS
2
2
2
2
2
2
2
2
19
18
16
14
17
15
13
20
/ WDTCLK
/ WDTCLK
/ WDTCLK
/ WDTCLK
/ WDTCLK
WDCS2 WDCS1 WDCS0
/ WDTCLK
/ WDTCLK
/ WDTCLK
overflow
Internal bus
WDTM
13
RUN
and 2
Output
control
circuit
WDTMODE
20
Watchdog Timer (WDT)
times the period of the
reset
NMIWDT
RESWDT
SYSRESWDT