upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 228

• Manufacturer Part Number: upd70f3422gj-gae-qs-ax
• Description: 32-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

Chapter 5
228
Maximum
Minimum
Interrupt response time (internal system clocks)
Figure 5-16
Table 5-4
Interrupt acknowledgement operation
Internal interrupt
Note
Note
5.9 Periods in Which Interrupts Are Not Acknowledged
Instruction (first instruction of
11
5
interrupt service routine)
Pipeline operation at interrupt request acknowledgment (outline)
INT1 to INT4: Interrupt acknowledgement processing
IFx:
IDx:
If the same interrupt occures during the interrupt acknowledge time of 5 cycles,
this new interrupt will discarded. The next interrupt of the same source will only
be registered after these 5 cycles.
Interrupt response time
An interrupt is acknowledged while an instruction is being executed. However,
no interrupt will be acknowledged between an interrupt non-sample instruction
and the next instruction.
The interrupt request non-sampling instructions are as follows:
• EI instruction
• DI instruction
• LDSR reg2, 0x5 instruction (for PSW)
• The store instruction for the interrupt control register (PlCn), in-service
Preliminary User’s Manual U17566EE1V2UM00
priority register (ISPR), and command register (PRCMD).
Interrupt request
VBCLK (Input)
Instruction 1
Instruction 2
11 + analog delay time
5 + analog delay time
Invalid instruction fetch
Invalid instruction decode
External interrupt
IF
IFX IDX
ID
5 system clocks
EX MEM WB
The following cases are exceptions:
• In IDLE/software STOP mode
• External bit access
• Two or more interrupt request non-
• Access to interrupt control register
INT1 INT2 INT3 INT4
sample instructions are executed
IF
Interrupt Controller (INTC)
ID
Condition
EX