upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 131

• Manufacturer Part Number: upd70f3422gj-gae-qs-ax
• Description: 32-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

Clock Generator
SPCLK clocks
PCLK clocks
IICLK clock
Table 4-1
(1)
(2)
(3)
CPU clocks
The CPU can be clocked directly by any of the oscillators, or by the output of
one of the PLLs.
The following table gives an overview of the available CPU clocks.
Clock sources and frequencies for the CPU
a)
b)
Peripheral clocks
The right-hand side of Figure 4-1 on page 130 shows how the clocks for the
peripheral modules are generated and distributed.
The PCLK clocks supply following peripherals: the CAN Controllers CAN, the
UARTs, the Timers Z, the Watch Calibration Timer, and the Clocked Serial
Interfaces CSIB.
The clocks PCLK0…1 can be derived from the main oscillator or the PLL
output. The PCLK2…15 clocks are always derived from the main oscillator.
The SPCLK clocks supply following peripherals: Stepper Motor Controller/
Driver, the Timer G, the Sound Generator, the Clocked Serial Interfaces CSIB,
the LCD Bus I/F and Controller/Driver, and A/D Converter ADC.
The clocks SPCLK0…1 can be derived from the main oscillator or the PLL.
The SPCLK2…15 clocks are always derived from the main oscillator.
The clock IICLK for the I
PLL.
Special clocks
The figure shows also some special clock signals. These are dedicated clocks
for the LCD Controller/Driver, Watch Timer, Watchdog Timer, and Watch
Preliminary User’s Manual U17566EE1V2UM00
Clock source Frequency
Ring osc
Sub osc
Main osc
PLL
SSCG
See also “CPU operation after power save mode release” on page 181
Multiplication is performed by the SSCG, the division by the SSCG post scaler.
~240 KHz
32 KHz
4 MHz
16 MHz
32 MHz
8 MHz
16 MHz
24 MHz
32 MHz
48 MHz
2
C interface is supplied by the main oscillator or the
Description
clock source for Sub-WATCH mode release.
Selectable as clock source for Sub-WATCH mode
release.
Always selected after power save mode release except
on Sub-WATCH mode release or default clock setting.
On Sub-WATCH mode release or default clock setting,
main or sub oscillator can be selected.
f
f
f
f
f
f
Default clock source after reset release. Selectable as
f
main
main
main
main
main
main
main
× 4 can be selected for CPU clock supply.
× 8 can be selected for CPU clock supply.
× 12/6
× 16/4
× 12/2
× 16/2
× 12/1
b
b
b
b
b
can be selected for CPU clock supply.
can be selected for CPU clock supply.
can be selected for CPU clock supply.
can be selected for CPU clock supply.
can be selected for CPU clock supply.
Chapter 4
131
a