upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 407
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upd70f3422gj-gae-qs-ax
Manufacturer Part Number
upd70f3422gj-gae-qs-ax
Description
32-bit Single-chip Microcontroller
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.UPD70F3422GJ-GAE-QS-AX.pdf
(930 pages)
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16-bit Timer/Event Counter P (TMP)
TPnOPT0
TPnIOC2
TPnIOC1
0
0
0
(d) TMPn I/O control register 1 (TPnIOC1)
(e) TMPn I/O control register 2 (TPnIOC2)
(f) TMPn option register 0 (TPnOPT0)
(g) TMPn counter read buffer register (TPnCNT)
(h) TMPn capture/compare registers 0 and 1 (TPnCCR0 and TPnCCR1)
Preliminary User’s Manual U17566EE1V2UM00
0
0
0
The value of the 16-bit counter can be read by reading the TPnCNT
register.
These registers function as capture registers or compare registers
depending on the setting of the TPnOPT0.TPnCCSm bit.
When the registers function as capture registers, they store the count value
of the 16-bit counter when the valid edge input to the TIPnm pin is
detected.
When the registers function as compare registers and when D
the TPnCCRm register, the INTTPnCCm signal is generated when the
counter reaches (D
inverted.
TPnCCS1
0/1
0
0
TPnCCS0
0/1
0
0
TPnEES1
m
0/1
0
+ 1), and the output signal of the TOPnm pin is
TPnIS3
0/1
TPnEES0 TPnETS1 TPnETS0
0/1
0
TPnIS2
0/1
0
0
TPnIS1
0/1
TPnOVF
0/1
0
TPnIS0
0/1
Overflow flag
Specifies if TPnCCR0
register functions as
capture or compare register
Specifies if TPnCCR1
register functions as
capture or compare register
Select valid edge of
external event count input
Select valid edge
of TIPn0 pin input
Select valid edge
of TIPn1 pin input
m
Chapter 11
is set to
407
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