upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 494

• Manufacturer Part Number: upd70f3422gj-gae-qs-ax
• Description: 32-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

Chapter 14
494
INTWT0UV
INTTM00
Setup example
WCTCLK
OVF00
CR000
TM00
Figure 14-4
14.5.1 INTWT0UV interval measurement with free-running counter
T
Note
0000
WCTCLK
H
0001
When the timer is used as a free-running counter (see register TMC00) and it
detects the valid edge of INTWT0UV, it
• copies the present counter value of register TM00 to CR000,
• generates the interrupt request INTTM00.
The valid edge (rising edge, falling edge) is specified in register PRM00. If both
edges are specified, CR000 cannot perform a capture operation.
TMC00 = 0000 0100
CRC00 = 0000 0x11
PRM00.ES00[1:0] = 01
The following figure is not to scale but illustrates the operation.
Timing in free-running mode
As shown in the figure, the interrupt INTTM00 can be used as a trigger for
reading the register CR000.
The interval duration must be calculated from the difference between the
present and the previous value of CR000.
If TM00 overflows between two occurrences of INTWT0UV, that means
between two capture triggers, the overflow flag TMC00.OVF00 is set.
Therefore, check also TMC00.OVF00 when reading the second capture value
in order to calculate the interval correctly, because an overflow may happen
during the measurement.
Consider the chosen periods for INTWT0UV and of WCTCLK.
Preliminary User’s Manual U17566EE1V2UM00
H
D0 D0 + 1
(D1 − D0) × T
D0
WCTCLK
B
B
:
:
D1
B
:
D1
(10000
D1 + 1
H
− D1 + D2) × T
Free running mode
CR000 as capture register with
INTWT0UV as capture signal
Rising edge
FFFF
H
0000
WCTCLK
H
D2
(D3 − D2) × T
D2
Watch Timer (WT)
WCTCLK
D3
D3