upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 842

• Manufacturer Part Number: upd70f3422gj-gae-qs-ax
• Description: 32-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

Chapter 24
842
SG0CLK =
(16MHz)
PCLK0
Tone generator
Figure 24-1
frequency low register
Outputs
SG0FL
24.1.1 Description
PWM
SG0CTL.PWR
1
0
The following figure provides a functional block diagram of the Sound
Generator.
Sound Generator block diagram
The Sound Generator's input clock SG0CLK is the 16 MHz clock PCLK0.
The tone generator consists of two up-counters with compare registers. The
values written to the frequency registers are automatically copied to compare
buffers. The counters are reset to zero when their values match the contents of
the associated compare buffers.
The 9-bit counter SG0FL generates a clock with a frequency between 32 KHz
and 64 KHz. This clock constitutes the PWM frequency.
It is also the input of the second 6-bit counter SG0FH. The resulting tone signal
behind the by-two-divider has a frequency between 245 Hz and 6 KHz and a
50 % duty cycle.
The PWM modulates the duty cycle according to the desired volume. It is
controlled by the volume register SG0PWM. The value written to this register is
automatically copied to the associated volume compare buffer.
The PWM continually compares the value of the counter SG0FL with the
contents of its volume compare buffer.
The RS flipflop of the PWM is set by the pulses generated by the counter
SG0FL. It is reset when the SG0FL counter value matches the contents of the
volume buffer. Thus, the PWM output signal can have a duty cycle between
0 % (null volume) and 100 % (maximum volume).
The PWM frequency is above 32 KHz and hence outside the audible range.
The Sound Generator is connected to the pins SGO and SGOA. By default, pin
SGO provides the tone signal SG0OF and pin SGOA the PWM signal SG0OA
that holds the volume (“amplitude”) information.
If bit SG0CTL.OS is set, pin SGO provides the composite signal SG0O that
can directly control a speaker circuit.
Preliminary User’s Manual U17566EE1V2UM00
volume compare buffer
frequency compare buffer
volume register
frequency counter
9-bit S0GFL
Clear
SG0PWM
SG0PWM
SG0FL
Match
CPU write to
SG0PWM
Match
Load
Load
= 0?
(32 to 64 kHz)
&
Y
f
&
PWM
Load
frequency high register
tone compare buffer
(32 to 64 kHz)
Tone
9-bit S0GFH
6-bit S0GFH
Clear
tone counter
f
SG0FH
SG0FH
PWM
Match
(490 Hz to
PWM
2 x f
12 kHz)
S
R
Tone
Reset
RS-FF
Tone
/2
Sound Generator (SG)
&
(245 Hz to
SG0OA
SG0OF
6 kHz)
f
(min. 32 kHz)
Tone
SG0
SG0CTL.OS
f
PWM
0
1
SG0A
SGO