upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 597

• Manufacturer Part Number: upd70f3422gj-gae-qs-ax
• Description: 32-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

I
2
C Bus (IIC)
Figure 18-9
SDA0n
SCL0n
the ACKEn bit to 0 will prevent the master device from starting transmission of
the subsequent data.
Similarly, when the master device is receiving (when TRCn bit = 0) and the
subsequent data is not needed and when either a restart condition or a stop
condition should therefore be output, clearing the ACKEn bit to 0 will prevent
the ACK signal from being returned. This prevents the MSB from being output
via the SDAn line (i.e., stops transmission) during transmission from the slave
device.
ACK signal
When the local address is received, an ACK signal is automatically output in
synchronization with the falling edge of the SCLn pin’s eighth clock regardless
of the value of the ACKEn bit. No ACK signal is output if the received address
is not a local address.
The ACK signal output method during data reception is based on the wait
timing setting, as described below.
When 8-clock wait is selected (IICCn.WTIMn bit = 0):
When 9-clock wait is selected (IICCn.WTIMn bit = 1):
Preliminary User’s Manual U17566EE1V2UM00
The ACK signal is output at the falling edge of the SCLn pin’s eighth clock if
the ACKEn bit is set to 1 before wait cancellation.
The ACK signal is automatically output at the falling edge of the SCLn pin’s
eighth clock if the ACKEn bit has already been set to 1.
AD6
1
AD5
2
AD4
3
AD3
4
AD2
5
AD1
6
AD0
7
R/W ACK
8
9
Chapter 18
597