upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 145

• Manufacturer Part Number: upd70f3422gj-gae-qs-ax
• Description: 32-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

Clock Generator
Bit position
6 to 5
4 to 3
2 to 0
Initial Value
calculation
Frequency
Table 4-8
Table 4-9
Address
Access
Note
(1)
a)
SCFC0 - SSCG frequency control register 0
The 8-bit SCFC0 register controls the frequency modulation of the SSCG. It
determines the SSCG output frequency and is used in conjunction with
register SCFC1.
The center SSCG output frequency is f
register defines the divisor “m” and thus M = m + 1.
This register can be read/written in 8-bit or 1-bit units.
FFFF F82C
52
a)
SCFC0 register contents
1.
2.
If dithering mode is disabled (CKC.DEN = 0) the SSCG outputs it’s center
frequency f
where:
• M = m + 1 = SCFC0.SCFC0[2:0] + 1
• N = n + 1 = SCFC1.SCFC1[6:0] + 1
The values to be written into SCFC0 and SCFC1 are restricted. Possible
combinations are:
Supported settings of N (n) and M (m)
Preliminary User’s Manual U17566EE1V2UM00
H
R/W
. The register is initialized by any reset.
This register can only be rewritten with a new value if the SSCG is
switched off. Refer to the explanation at the beginning of this section.
The inital value of this register must be changed after reset.
f
0
7
SCFC0[6:5]
SCFC0[4:3]
SCFC0[2:0]
SSCGc
a
In this mode the 64 MHz SSCG output frequency has to be devided by the SSCG
post scaler. Thus set SCPS = 21
tion.
The default value “0” of this bit must not be altered.
Bit name
f
SSCGmax
64 MHz
48 MHz
= (4 MHz x N/M) / 2
SSCGc
SCFC06
H
R/W
.
a
6
:
SCFC05
Function
Must be set to 01
Must be set according to Table 4-9
Determines the divisor m
R/W
5
M (m)
4 (3)
3 (2)
SCFC04
R/W
4
H
for 32 MHz or SCPS = 23
96 (95)
96 (95)
B
N (n)
SSCGc
SCFC03
R/W
3
= (4 MHz × N/M) / 2. This
SCFC02
R/W
SCFC0
2
2B
32
H
H
H
SCFC01
for 16 MHz opera-
R/W
1
SCFC1
Chapter 4
DF
DF
SCFC00
R/W
H
H
0
145