upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 388

• Manufacturer Part Number: upd70f3422gj-gae-qs-ax
• Description: 32-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

Chapter 11
388
External trigger input
INTTPnCC0 signal
INTTPnCC1 signal
TPnCCR0 register
TPnCCR1 register
TOPn0 pin output
TOPn1 pin output
(TIPn0 pin input)
16-bit counter
Figure 11-19
TPnCE bit
FFFFH
0000H
Basic timing in one-shot pulse output mode
When the TPnCE bit is set to 1, 16-bit timer/event counter P waits for a trigger.
When the trigger is generated, the 16-bit counter is cleared from FFFFH to
0000H, starts counting, and outputs a one-shot pulse from the TOPn1 pin.
After the one-shot pulse is output, the 16-bit counter is set to FFFFH, stops
counting, and waits for a trigger. If a trigger is generated again while the one-
shot pulse is being output, it is ignored.
The output delay period and active level width of the one-shot pulse can be
calculated as follows.
Output delay period = (Set value of TPnCCR1 register) × Count clock cycle
Active level width =
(Set value of TPnCCR0 register – Set value of TPnCCR1 register + 1) × Count clock cycle
The compare match interrupt request signal INTTPnCC0 is generated when
the 16-bit counter counts after its count value matches the value of the CCR0
buffer register. The compare match interrupt request signal INTTPnCC1 is
generated when the count value of the 16-bit counter matches the value of the
CCR1 buffer register.
The valid edge of an external trigger input or setting the software trigger
(TPnCTL1.TPnEST bit) to 1 is used as the trigger.
Preliminary User’s Manual U17566EE1V2UM00
Delay
(D
D
1
1
)
Active
level width
(D
D
0
0
− D
1
+ 1)
Delay
(D
D
1
0
)
Active
level width
(D
D
D
D
0
0
1
0
− D
16-bit Timer/Event Counter P (TMP)
1
+ 1)
Delay
(D
D
1
1
)
Active
level width
(D
D
0
0
− D
1
+ 1)