upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 589
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upd70f3422gj-gae-qs-ax
Manufacturer Part Number
upd70f3422gj-gae-qs-ax
Description
32-bit Single-chip Microcontroller
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.UPD70F3422GJ-GAE-QS-AX.pdf
(930 pages)
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I
2
C Bus (IIC)
Initial Value
Initial Value
Address
Address
Caution
Access
Access
(5)
(6)
IICXn - IICn function expansion registers
The IICXn registers provide additional transfer data rate configuration in fast-
speed mode. Setting of the IICXn.CLXn is performed in combination with the
IICCLn.SMCn, IICCLn.CLn[1:0], OCKSn.OCKSTHn and OCKSn.OCKSn[1:0]
(refer to “Transfer rate setting“ on page 590)
This register can be read/written in 8-bit or 1-bit units.
<base> + 5
00
OCKSn - IICn division clock select registers
The OCKSn registers control the I
This register can be read/written in 8-bit or 1-bit units.
<base> + 20
00
Bit of OCKSn must be set to “1” after reset and must not be changed
afterwards.
Preliminary User’s Manual U17566EE1V2UM00
OCKSTHn
H
H
R/W
R/W
. This register is cleared by any reset.
. This register is cleared by any reset.
7
0
7
0
0
0
0
0
1
Other than above
H
H
R/W
R/W
6
0
6
0
OCKSn1
0
0
1
1
0
R/W
R/W
5
0
5
0
OCKSn0
0
1
0
1
0
R/W
R/W
4
0
4
1
2
Cn division clock.
Output clock IICLKPS
IICLK/2
(Only allowed if 4MHz IICLK is used!)
IICLK/3
IICLK/4
IICLK/5
IICLK
(Only allowed if 4MHz IICLK is used!)
Setting prohibited
OCKSTHn
R/W
R/W
3
0
3
R/W
R/W
2
0
2
0
OCKSn1
R/W
R/W
1
0
1
Chapter 18
OCKSn0
CLXn
R/W
R/W
0
0
589
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